Assignment 2

Section 02: Due  10/9 at the start of class

  1. (3 points) By combining a 3-bit counter with an 8 to 1 multiplexer, it is possible to make a parallel to serial converter. Design such a 3-bit counter and show how it would be connected to the multiplexer. You must draw the complete circuit for the counter, including any memory needed to store the current count. Every time the clock goes low, the counter should be incremented by one. You may draw a block diagram for the multiplexer. (Hint: You may only need half of what you think you need.) You may only use the circuits we have discussed in class. You will receive no credit if you use other circuits.

  2. (2 points) On many CPUs there are condition codes to test if the answer was zero, and to test if there was signed overflow: Z and O. An 8-bit ALU is constructed from 8 1-bit ALUs in Fig. 3-20. How would each of these condition codes be wired to such an ALU? Draw the circuits for each. (The O bit is set when the carry into the highest ALU is different from the carry out of the highest ALU). Remember that Fig. 3-20 is difficult to read. Please refer to my lecture when I explained the diagram.

  3. (3 points)
    1. Draw a truth table for the following circuit. In the truth table, assume that C != D and E != F and A = B = 1. In the table, show the effect on C,D,E, and F when the clock changes from low to high. Also indicate what happens to them when the clock changes from high to low.
      hw2 diagram
    2. Why does this design have two memory circuits? In other words, what would happen if there was only one?

  4. (3 points) The 4 X 3 memory of Figure 3-29 uses 22 AND gates and three OR gates. It also has 11 input, output, and control lines.
    1. Suppose the circuit were expanded to 256 x 64.
      1. How many AND gates would be needed?
      2. How many OR gates would be needed?
      3. How many pins would be coming into and out of the chip?
    2. Suppose the circuit were expanded to 512 x 32.
      1. How many AND gates would be needed?
      2. How many OR gates would be needed?
      3. How many pins would be coming into and out of the chip?

  5. (2 points) Figure 3-44 lists the pinout for the Pentium II. Figure 3-52 lists the bus signals on the PCI bus. By reading the descriptions of the pins and the signals in the text, make an educated guess as to which Pentium II pins would correspond to the following PCI bus signals?
    1. FRAME#
    2. IDSEL#
    3. DEVSEL#
    4. TRDY#

  6. (3 points) Complete the following table
    Processor Size of L2 Cache Width of Memory Bus A unique feature
    (not already listed here)
    Pentium II      
    ultraSparc II      
    picoJava II      

  7. (1 point) Referring to the timing diagram of Fig, 3-37, suppose that you slowed the clock down to 20 MHz instead of 40 MHz, but the timing constraints  in the table remained unchanged. How much time would the memory have from the assertion of !MREQ to the moment that the data first appears on the bus during T3?

  8. (3) In section 3.7.2, assume that the memory space is 128K; the EPROM is 2K in size and will be placed at address 110K; the RAM is 4k in size and will be placed at address 40K; the PIO is 4 bytes and will be placed starting at address 27K. Draw the circuit for the !CS lines into the devices. Use full address decoding.

  9. Optional. Draw a circuit using AND and OR gates, and only two INVERTERS that will  implement a decoder. You may use as many AND and OR gates as needed. You may not use any other circuits, such as NAND, NOR, XOR.