Fall 2002, Computer Organization, Assignment 3

Section 02: Due Monday 11/18 at the start of class

Type all the answers. Hand in a printout. Upload the assignment via the web: Submitting Homework Online.

  1. (2) What is the Micro Assembly Language (MAL) instruction for this hex microinstruction?
    4413F2108
  2. (2) What is the hex microinstruction for this Micro Assembly Language (MAL) instruction?
    MAR = SP = SP + 1; wr; fetch; goto(0x13D)
  3. (2) Explain how it is possible that the goto(MBR) in instruction two has the MBR from the fetch in instruction one, but that MDR in instruction 4 is not the value from the read in instruction three.
    INST1: PC = PC + 1; fetch
    INST2: PC = PC + 1; fetch; goto(MBR)
    INST3: MAR = SP - 1; rd
    INST4: H = MDR
  4. (1) What would be the byte code for the instruction:
    GOTO  -45 
  5. (1) The PC and the MAR both hold addresses. There is a difference between how these addresses are used in their respective caches. Explain the difference.
  6. (2) Translate the following statement into IJVM symbolic instructions (like IADD, BIPUSH, etc). Use reasonable values for I, J, and K. Assume that  the offset of CALCULATE in the constant pool is 0x1234. Since we are not implementing object oriented calls, assume that this (the pointer to the current object) is 0 (NULL). 
    K = CALCULATE(I, J);
  7. (1) Explain how a large PLA could be used instead of a ROM to implement the control store. Assume the PLA is as big as you need it to be.
  8. (3) IJVM versus JVM
    1. In the IJVM, the first instruction for DUP is at 0x59 in the ROM. Why can't the second instruction for DUP be at address 0x60 in our IJVM?
    2. Assuming that the full JVM has 256 op codes, what can you surmise about the size of the ROM in the full JVM. Explain your answer.
    3. Assuming that the full JVM has 256 op codes, what might be a plausible address for the address of Main1 in the ROM?
  9. (2) Write the microcode for an IFLE instruction. It pops the top operand from the stack and branches if the top operand is less than or equal to zero. Remember that the ALU sets the condition codes during every instruction. Be sure that your jump addresses are consistent within IFLE and within the remaining microinstructions.
  10. (2) Implement WIDE IINC. It is just like IINC except that both the varnum and the constant are 16 bits.
  11. (2) There are four improvements from MIC-1 to MIC-2: a) 3 bus architecture,  b) instruction fetch unit handles the PC, c) access to 16-bit operands and d) merging the interpreter loop. INVOKEVIRTUAL in MIC-1 has 22 lines of code, it has 11 lines of code in MIC-2. There are three types of changes: sequences of instructions are grouped into one instruction; instructions are removed, instructions are changed. For the MIC-1 INVOKEVIRTUAL command, indicate which instructions are removed, which are grouped, and which are changed. For each, indicate the improvement(s) that allowed the alteration. If they are grouped, indicate which instructions are grouped together.