Assignment 2

Due  9/30 at the start of class

1. (2 points) On many CPUs there are condition codes to test if the answer was zero, and to test if there was signed overflow: Z and O. An 8-bit ALU is constructed from 8 1-bit ALUs in Fig. 3-20. How would each of these condition codes be wired to such an ALU? Draw the circuits for each. (The O bit is set when the carry into the highest ALU is different from the carry out of the highest ALU). Remember that Fig. 3-20 is difficult to read. Please refer to my lecture when I explained the diagram.
   
   
2. (3 points)
   1. Draw a circuit of an SR latch that uses two NAND gates instead of two NOR gates. Label the two inputs as A and B.
   2. Categorize as queiescent (unchanged), unstable, set, reset or any other suitable description for the following values for A and B.
      1. A = 0 B = 0
      2. A = 1 B = 1
      3. A = 0 B = 1
      4. A = 1 B = 0
         
         
3. (2 points) The 4 X 3 memory of Figure 3-29 uses 22 AND gates and 3 OR gates.
   1. Suppose the circuit were expanded to 1024 x 32.
      1. How many AND gates would be needed?
      2. How many OR gates would be needed?
         
         
4. (2 points) Figure 3-44 lists the pinout for the Pentium II. Figure 3-52 lists the bus signals on the PCI bus. By reading the descriptions of the pins and the signals in the text, make an educated guess as to which Pentium II pins would correspond to the following PCI bus signals?
   1. FRAME#
   2. C/BE
   3. DEVSEL#
   4. TRDY#
      
      
5. (1 point) On page 172 of the book, there is the following statement:
   Addresses are 36 bits, but the loworder bits must always be 0...
   Explain why this statement is true.
   
   
6. (3 points) Complete the following table
   

   Processor	Size of L2 Cache	Width of Data Bus	Number of Transistors
   Pentium II
   ultraSparc II
   picoJava II

7. (1 point) Referring to the timing diagram of Fig, 3-37, suppose that you sped the clock up to 66 MHz instead of 40 MHz, but the timing constraints  in the table remained unchanged. How much time would the memory have from the assertion of !MREQ to the moment that the data first appears on the bus during T3?
   
   
8. (3) In section 3.7.2, assume that the memory space is 32K; the EPROM is 4K in size and will be placed at address 12K; the RAM is 2k in size and will be placed at address 20K; the PIO is 4 bytes and will be placed starting at address 29K. Draw the circuit for the !CS lines into the devices. Use full address decoding.
   
   
9. (3) The diagram on page 186 shows the layout for the PCI Arbiter. The arbitration scheme is unspecified. Inside the box labeled "PCI Arbiter", implement a Round Robin scheme. In Round Robin arbitration, if a device is granted the bus, but didn't request it, then the device grants access to the next device in line. If the device is granted the bus and requested it, then it takes control of the bus and uses it. Here is the Round Robin part: the next device after the device that actually uses the bus (not necessarily the device that was first granted the bus), gets the first chance to use the bus in the next round. Remember that if a device is granted the bus, but didn't request it, then the grant is passed to the next device. You may use a block diagram for a 2:4 decoder, a 4:2 encoder, and a 2-bit counter.

Course Objectives met by this Homework