Fall 2003, Computer Organization, Assignment 4

Due Thursday 11/13 at the start of class

Type all the answers. Hand in a printout. Upload the assignment via the web: Submitting Homework Online.

1. (2) What is the Micro Assembly Language (MAL) instruction for each of these hex microinstructions?
   1. 948248027
   2. 7897F2148
2. (2) What is the hex microinstruction for each of these Micro Assembly Language (MAL) instructions? You must make up suitable addressed for ADDR1, ADDR2, and ADDR3.
   1. MAR = SP = SP + 1; wr; fetch; goto(ADDR1)
   2. H = MBRU OR H << 8; goto (MBR OR 0x111)
3. (1) Explain how it is possible that the goto(MBR) in instruction 2 has the MBR from the fetch in instruction 1, but that MDR in instruction 4 is not the value from the read in instruction 3.
   INST1: PC = PC + 1; fetch
INST2: PC = PC + 1; fetch; goto(MBR)
INST3: MAR = SP - 1; rd
INST4: H = MDR
4. (1) What would be the byte code for the instruction:
   GOTO  -118 
5. (1) The PC and the MAR both hold addresses. There is a difference between how these addresses are used in their respective caches. Explain the difference.
6. (2) Translate the following statement into IJVM symbolic instructions (like IADD, BIPUSH, etc). Use reasonable values for I, J, and K. Assume that  the offset of CALCULATE in the constant pool is 0x1234. Since we are not implementing object oriented calls, assume that this (the pointer to the current object) is 0 (NULL).

   K = CALCULATE(I, J);
       
   

7. (1) Explain how a large PLA could be used instead of a ROM to implement the control store. Assume the PLA is as big as you need it to be.
8. (2) IJVM versus JVM
   1. In the IJVM, the first instruction for  LDC_W is at address 0x13 in the ROM. Why can't the remaining instructions for LDC_W be at addresses 0x14, 0x15, and 0x16 in our IJVM?
   2. Assuming that the full JVM has 256 op codes, what might be a plausible address for the address of Main1 in the ROM?
9. (2) Write the microcode for an IFGT instruction in Mic-1. It pops the top operand from the stack and branches if the top operand is greater than zero. Remember that the ALU sets the condition codes during every instruction. Be sure that your jump addresses are consistent within IFGT and within the remaining microinstructions.
10. (2) Implement DLOAD in Mic-1. It is just like ILOAD except that it pushes two consecutive local variables onto the stack.
11. (4) There are four improvements from MIC-1 to MIC-2: a) 3 bus architecture,  b) instruction fetch unit handles the PC, c) access to 16-bit operands and d) merging the interpreter loop. INVOKEVIRTUAL in MIC-1 has 22 lines of code, it has 11 lines of code in MIC-2. There are three types of changes: sequences of instructions are grouped into one instruction; some instructions are removed, some instructions are modified. For the MIC-1 INVOKEVIRTUAL command, indicate which instructions are removed, which are grouped, and which are modified. For each, indicate which of the three improvements allowed the alteration. If they are grouped, indicate which instructions are grouped together.

Course Objectives met by this Homework