CDA-4101 Section 01, Fall 2003 Syllabus

Homework Grading Policy
Each assignment		0 to 20 points
Exams and Assignments
	Exam 1	Exam 2	Homework
% of Grade	35%	35%	30%
Dates	Tuesday, 10/14	Thursday, 12/11 (930 - 1215)	Various
Text
Structured Computer Organization, Fourth Edition, Andrew S. Tannebaum, Prentice Hall, Fourth Edition
Room and Time
Room ECS136;TR 1100-1215

Attendance I recommend that you attend every class. Those who attend class have a better chance of passing the course.

Prerequisites MAD 2104, COP 3402, COP 3337

Late Assignment Policy Assignments are due at the START of class. You lose 1 point off the grade for every 6 hours. You may hand in a nassignment up to 1 week late, I will start the grading for very late assignments at 12 points (60%).

Working Together on Assignments is NOT ALLOWED. There is a large difference between discussing general aspects of the course and discussing specific aspects of an assignment. Do not discuss your solution of a problem with others. Assignments that are too similar will not be graded. With a second occurrence, you will earn an F in the course.

Course Content

• Review: Multilevel Computers
  • The Digital Logic Level
  • The Microarchitecture Level
  • The Instruction Set Architecture Level
  • The Operating System Level
  • The Assembly Language Level
  • Computer Families
    • Pentium II
    • UltraSPARC II
    • picoJava II
• Organization
  • Processors
  • RISC vs CISC
  • Instruction-level parallelism
    • Pipelining
    • Superscalar
  • Processor-level parallelism
    • Array Computers
    • Vector
    • Multiprocessors
    • Multicomputers
• The Digital Logic
  • Level Gates and Boolean Algebra
  • Basic Digital Logic
  • Circuits
  • Memory
  • CPU Chips
  • Buses
  • I/O Chips
• The Microprogramming Level
  • An Example Microarchitecture
  • An Example Macroarchitecture (ISA)
  • An Example Microcode
  • Design of the Microarchitecture Level
  • Improving Performance
  • Examples of the Microarchitecture Level
• Machine Level
  • IA-64
• Assembly Level
  • Linking and loading
• Multicomputers
  • Shared-memory
  • Message-passing
  • Cache-coherence
  • Parallel computers

Course Objectives

• Be exposed to the hierarchy of virtual machines in a computer system
• Be familiar with the CPU instruction execution cycle
• Master the design of memory, ALU, control unit, and design of microprogram
• Be familiar with cache architectures, branch predictions and scheduling of multiple instruction issue
• Be familiar with instruction set architecture, interrupts, and traps
• Be familiar with CISC and RISC architectures, and parallel computer configurations
• Be exposed to shared-memory and message-passing multicomputers, and cache coherence protocols