CDA4101, Assignment 2

Due Sunday, 3/22 (not late until 6 am 3/23)

(5 points) By combining a 3-bit counter with an 8 to 1 multiplexer, it is possible to make a parallel to serial converter. Design such a 3-bit counter and show how it would be connected to the multiplexer. You must draw the complete circuit for the counter, including any memory needed to store the current count. Every time the clock goes low, the counter should be incremented by one. You may draw a block diagram for the multiplexer. (Hint: You may only need half of what you think you need.) You may only use the circuits we have discussed in class. You will receive no credit if you use other circuits.
(4 points) On many CPUs there are condition codes to test if the answer was zero, and to test if there was signed overflow: Z and O. An 8-bit ALU is constructed from 8 1-bit ALUs in Fig. 3-19. How would each of these condition codes be wired to such an ALU? Draw the circuits for each. (The O bit is set when the carry into the highest ALU is different from the carry out of the highest ALU). Fig. 3-19 is difficult to read. Please refer to my lecture when I explained the diagram.
(3 points)
1. Draw a truth table for the following circuit. In the truth table, assume that C != D and E != F and A = B = 1. Only include valid combinations of input in the truth table (only 8 rows are needed in the table). First, show what happens to C and D when the clock is high. Then show what happens to E and F when the clock goes low, based on the new values of C and D.
2. Summarize what happens to E when the clock changes from high to low, and A = B = 1.
(4) Calculate the bus bandwidth to display 1280x1024 full-color video at 30 frames/sec. Assume that the data must pass over the buse twice, once from the CD-ROM to the memory and once from the memory to the screen.
(1) What is the quiescent state of the S and R inputs to an SR latch built from two NAND gates?
(4) A PCI Express system has 10 Mbps lanes (gross capacity, one way). How many signal wires are needed in one direction for 16x operation? What is the gross capacity one way (MBps)? What is the net capacity one way (MBps)?
(6 points) The 4 X 3 memory of Figure 3-29 uses 22 AND gates and three OR gates. It also has 11 input, output, and control lines.
1. Suppose the circuit were expanded to 256 x 64.
  1. How many AND gates would be needed?
  2. How many OR gates would be needed?
  3. How many pins would be coming into and out of the chip?
2. Suppose the circuit were expanded to 512 x 32.
  1. How many AND gates would be needed?
  2. How many OR gates would be needed?
  3. How many pins would be coming into and out of the chip?
(4) Referring to the timing diagram of Fig, 3-38, suppose that you slowed the clock down to 80 MHz instead of 100 MHz, but the timing constraints in the table remained unchanged. How much time would the memory have from the assertion of !MREQ to the moment that the data first appears on the bus during T3? Show all calculations.
(3) Assume DMA is being used to read all 2048 sectors of 512-bytes each in a track on a disk. Each 32-bit DMA transfer takes 1 bus cycle of 10 nsec. It takes one rotation of 5 msec to read the entire track. How many cycles per millisecond is the DMA master stealing from the CPU?
(3) A PCI Express system has 10 Mbps lanes (gross capacity). How many signal wires are needed in one direction for 16x operation? What is the gross capacity (MBps) one way? What is the net capacity one way (MBps)?
(2) The maximum payload of an isochronous data packet on USB version 1.0 is 1023 bytes. Assuming that a device may send only one data packet per frame, what is the maximum bandwidth (in MBps) for a sinlge isochronous device?
(5) In section 3.7.2, assume that the memory space is 16K; the EPROM is 2K in size and will be placed at address 14K; the RAM is 4k in size and will be placed at address 10K; the PIO is 4 bytes and will be placed starting at address 5K. Draw the circuit for the !CS lines into the devices. Use full address decoding.