CDA4101 Section
Structured Computer Organization

Office

Room: ECS 341

Phone: (305) 348-3329 (FIU-D-DAY)

Regular mail: My mailbox is in the ECS building, 3rd floor, Computer Science, room 354

Office Hours

Mon, Wed

3:30-4:30pm; 6:30-7:30pm

Fri

12:00pm-5:00pm

Internet Information

E-mail: downeyt

	At Least Four Extra Credit Assignments
Weight	One point of extra credit each (possibly more)
	Four Homework Assignments
Weight	12.5 points each
	Four Exams
Weight	40 points each
Grading Scale
The grade for the course will based on the following scale. The scale is based on the sum of your scores on the tests, homework and extra credit.
Scale	A: 189; A-: 180.5; B+: 172; B: 163.5; B-: 155; C+: 146.5; C: 138; C-: 129.5; D+: 121; D: 112.5; D-: 104
Text
	Structured Computer Organization, 6/E Tannenbaum, Andrew S. ISBN-10: 0132916525; ISBN-13: 9780132916523
Room and Time

Course Content

Review: Multilevel Computers
- The Digital Logic Level
- The Microarchitecture Level
- The Instruction Set Architecture Level
- The Operating System Level
- The Assembly Language Level
- Computer Families
  - Pentium II
  - UltraSPARC II
  - picoJava II
Organization
- Processors
- RISC vs CISC
- Instruction-level parallelism
  - Pipelining
  - Superscalar
- Processor-level parallelism
  - Array Computers
  - Vector
  - Multiprocessors
  - Multicomputers
The Digital Logic
- Level Gates and Boolean Algebra
- Basic Digital Logic
- Circuits
- Memory
- CPU Chips
- Buses
- I/O Chips
The Microprogramming Level
- An Example Microarchitecture
- An Example Macroarchitecture (ISA)
- An Example Microcode
- Design of the Microarchitecture Level
- Improving Performance
- Examples of the Microarchitecture Level
Machine Level
- IA-64
Assembly Level
- Linking and loading
Multicomputers
- Shared-memory
- Message-passing
- Cache-coherence
- Parallel computers

Master the design of memory, ALU, control unit, and design of microprogram
Be familiar with cache architectures, branch predictions and scheduling of multiple instruction issue
Be familiar with instruction set architecture, interrupts, and traps
Be familiar with CISC and RISC architectures, and parallel computer configurations
Be exposed to shared-memory and taxonomy of parallel architectures