Assignment 2

Due  5/24 at the start of class

  1. (2 points) On many CPUs there are 4 condition codes: N, Z, O, C to test if the result of the ALU operation was zero, negative, wrong as a signed number, wrong as an unsigned number, respectively. An 8-bit ALU is constructed from 8 1-bit ALUs in Fig. 3-20. How would each of these condition codes be wired to such an ALU? Draw the circuits for each. (The O bit is set when the carry into the highest ALU is different from the carry out of the highest ALU).
  2. (4 points) The shifter on page 136 only has two functions: shift right and shift left. Create a new circuit that implements a shifter with these four functions: arithmetic shift right, don't shift, rotate left, rotate right. The shifting done in the book is logical shifting: a 0 is placed into the S0 or S7 bit, depending on which way the shift goes. An arithmetic shift right places D0 into both S0 and S1: it is duplicating the sign bit. A don't shift operation would send each data bit to the corresponding output: D0 to S0, D1 to S1, etc. A rotate left operation will do a logical shift left and will move the D0 bit to S7. A rotate right operation will do a logical shift right and will move the D7 bit to S0.
  3. (3 points)
    1. Draw a circuit of an SR latch that uses two NAND gates instead of two NOR gates. Label the two inputs as A and B.
    2. Categorize as queiescent (unchanged), unstable, set, reset or any other suitable description for the following values for A and B.
      1. A = 0 B = 0
      2. A = 1 B = 1
      3. A = 0 B = 1
      4. A = 1 B = 0
  4. (3 points) The 4 X 3 memory of Figure 3-29 uses 22 AND gates and three OR gates. It also has 11 input, output, and control lines.
    1. Suppose the circuit were expanded to 256 x 64.
      1. How many AND gates would be needed?
      2. How many OR gates would be needed?
      3. How many pins would be coming into and out of the chip?
    2. Suppose the circuit were expanded to 512 x 32.
      1. How many AND gates would be needed?
      2. How many OR gates would be needed?
      3. How many pins would be coming into and out of the chip?
  5. (2 points) Sometimes it is useful for an 8-bit ALU such as Fig. 3-20 to generate the constant -1  (negative one) as output. Give two additional ways this can be done. For each way, specify the values of the six control signals: ENA, ENB, INVA, INC (carry into the lowest ALU), F0 and F1. Each of the ALUs gets the same values for ENA, ENB, INVA, F0, and F1. Only the lowest ALU gets INC. You may not control the values of A and B.
  6. (2 points) In round robin bus arbitration, each device gets the bus in turn: device 1, device 2, device 3, device 4, device 1, device 2, device 3, device 4 etc. Each time the arbiter grants the bus, if the device that receives the grant has not made a request, then the arbiter will grant the bus to the next device in line that did make a request. How could such an arbitration scheme be implemented? Design such a circuit using a centralized arbitration scheme. You may want to design a 2-bit adder that can count 00, 01, 10, 11, 00, 01, etc.
  7. (1 point) Referring to the timing diagram of Fig, 3-37, suppose that you slowed the clock down to 20 MHz instead of 40 MHz as shown but the timing constraints remained unchanged. How much time would the memory have to get the data onto the bus during T3 after NOT MREQ was asserted, in the worst case?
  8. (3) In section 3.7.2, assume that the memory space is 128K; the EPROM is 4K in size and will be placed at address 120K; the RAM is 2k in size and will be placed at address 36K; the PIO is 4 bytes and will be placed at address 5K. Write the boolean equations for the chip select pin for each chip, using full address decoding. Do not draw the circuit.
  9. Optional (If you don't already have credit for this). Draw a circuit using AND and OR gates, and only two INVERTERS that will invert its three inputs. You may use as many AND and OR gates as needed. You may not use any other circuits, such as NAND, NOR, XOR.