General Information for CDA-4101

• General course info
  • Syllabus
  • Daily topics. Last modified on
• Exam Information will be posted here prior to exams
  • Midterm: 5/25
  • Chapter 4 will not be on the midterm. Check the daily topics for a list of topics that were covered.
  • Final: Thursday 6/17.
• Assignments will be posted here
  • Submitting Homework Online.
  • Assignment 1, due on 5/13.
  • Assignment 2, due on 5/20.
  • Assignment 3, due on 4/3.
  • Data file dor assignment 3.
  • Assignment 4,due on 6/10.
  • Assignment 5, due on 6/16.
  • Assignment 5 solutions. Last modified on .
• Extra Information
  • 4-input Boolean function on the MSI multiplexer chip.
  • More information about the C and N bits when comparing numbers.
  • Decentralized Bus Arbitration
  • Implementation of the Majority function using the LSI PLA chip from page 95.
  • A great page for memory information
    • Information about memory sizes and parity
    • Memory technologies
    • Memory Speed and Access Timing
    • Video RAM
    • Memory Technology Types
  • Types of memory
  • Bus Arbitration
  • Hamming Code Program

Running the Hamming Code Program

I have written a program that will allow you to calculate a Hamming codeword using single-bit error correction with even-parity check bits. Run my CGI Hamming Program. This should work from any browser, including a text based browser like lynx.

It is also possible to run the program the old-fashioned way: log onto SOLIX! When you log onto SOLIX, change to the directory

        ~downeyt/public_html/cop2400

and from there run the hamming program by typing

        hamming_code

from the prompt.

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More Information on the N and C bits

• It is not possible to use the N bit alone to determine the relative order of unsigned numbers. Try to create the following examples:
  1. Perform A - B where the result is negative, and B > A as unsigned numbers
  2. Perform C - B where the result is positive, and B > C as unsigned numbers. Use the same value for B as in the first example.
• The C bit is implemented as I had described originally. It is set as if the subtraction were done without using the 2's complement of the number. Perform the subtraction as you would normally (not with 2's complement), if you need to borrow to complete the subtraction, then the carry bit will be set. This raises the question of how this would be implemented in hardware. One solution would be to negate the carry-out of the highest ALU whenever the ALU forms the 2's complement of the A bus.

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