Assignment 2

Section 01: Due  10/9 at the start of class
Section 02: Due  10/8 at the start of class

  1. (3 points) By combining a 3-bit counter with an 8 to 1 multiplexer, it is possible to make a parallel to serial converter. Design such a 3-bit counter and show how it would be connected to the multiplexer. You must draw the complete circuit for the counter, including any memory needed to store the current count. Every time the clock goes low, the counter should be incremented by one. You may draw a block diagram for the multiplexer. (Hint: You may only need half of what you think you need.)

  2. (4 points) The shifter on page 136 only has two functions: shift right and shift left. Create a new circuit that implements a shifter with four functions: arithmetic shift right, don't shift, rotate left, rotate right. The shifting done in the book is logical shifting: a 0 is placed into the S0 or S7 bit, depending on which way the shift goes. An arithmetic shift right places D0 into both S0 and S1: it is duplicating the sign bit. A don't shift operation would send each data bit to the corresponding output: D0 to S0, D1 to S1, etc. A rotate left operation will do a logical shift left and will move the D0 bit to S7. A rotate right operation will do a logical shift right and will move the D7 bit to S0.

  3. (1 point) Consider the following memory circuit. The left half of the circuit functions when the clock is high, the right half functions when the clock is low. What happens to the values at E and F when A=1, B=1 and the clock changes from high to low?

  4. (2 points) Figure 3-44 lists the pinout for the Pentium II. Figure 3-52 lists the bus signals on the PCI bus. By reading the descriptions of the pins and the signals in the text, indicate which Pentium II pins would correspond to the following PCI bus signals?
    1. FRAME#
    2. IDSEL#
    3. DEVSEL#
    4. TRDY#

  5. (3 points) Complete the following table
    Processor Size of L2 Cache Width of Memory Bus A unique feature
    (not already listed here)
    Pentium II      
    ultraSparc II      
    picoJava II      

  6. (3 points) In round robin bus arbitration, each device gets the bus in turn: device 0, device 1, device 2, device 3, device 0, device 1, device 2, device 3, device 0, etc. Each time the arbiter grants the bus, if the device that receives the grant has not made a request, then the arbiter will grant the bus to the first device in line that did make a request. The passing of the grant will happen within the same request cycle. How could such an arbitration scheme be implemented? Design such a circuit using a centralized arbitration scheme. You may use a block diagram to represent the 2-bit counter.

  7. (1 point) Referring to the timing diagram of Fig, 3-37, suppose that you slowed the clock down to 20 MHz instead of 40 MHz, but the timing constraints  in the table remained unchanged. How much time would the memory have from the assertion of !MREQ to the moment that the data first appears on the bus during T3?

  8. (3) In section 3.7.2, assume that the memory space is 128K; the EPROM is 2K in size and will be placed at address 110K; the RAM is 4k in size and will be placed at address 40K; the PIO is 4 bytes and will be placed starting at address 27K. Draw the circuit for the !CS lines into the devices. Use full address decoding.

  9. Optional (If you don't already have credit for this). Draw a circuit using AND and OR gates, and only two INVERTERS that will invert its three inputs. You may use as many AND and OR gates as needed. You may not use any other circuits, such as NAND, NOR, XOR. The important terms to generate are !A!BC, !AB!C, A!B!C, !A!B!C, !ABC, A!BC, AB!C, ABC.