Section 01: Due 10/9 at the start of class
Section 02: Due 10/8 at the start of class
(3 points) By combining a 3-bit counter with an 8 to 1 multiplexer, it is
possible to make a parallel to serial converter. Design such a 3-bit counter
and show how it would be connected to the multiplexer. You must draw the
complete circuit for the counter, including any memory needed to store the
current count. Every time the clock goes low, the counter should be incremented
by one. You may draw a block diagram for the multiplexer. (Hint: You may
only need half of what you think you need.)
(1 point) Do question 12 on page 200 of the text.
(1 point) Do question 13 on page 200 of the text.
(3 points) Do question 14 on page 200 of the text.
(2 points) Give a practical example of when the LOCK# pin would be needed
on the PII chip.
(3 points) Complete the following table
Processor
Size of L2 Cache
Width of Memory Bus
A unique feature
(not already listed here)
Pentium II
ultraSparc II
picoJava II
(3 points) Create the centralized arbiter that could be used on the PCI bus
that would implement 2-level daisy chaining. Refer to the diagram in the
book for the PCI bus arbiter.
(1 point) Referring to the timing diagram of Fig, 3-37, suppose that you
slowed the clock down to 25 MHz instead of 40 MHz, but the timing
constraints in the table remained unchanged. How much time would the
memory have from the time that the address is stable to the moment that
the data first appears on the bus?
(3) In section 3.7.2, assume that the memory space is 128K; the EPROM is
8K in size and will be placed at address 112K; the RAM is 4k in size and
will be placed at address 96K; the PIO is 4 bytes and will be placed starting
at address 39K. Draw the circuit for the !CS lines into the devices. Use
full address decoding.