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I attest that I have done all of this work on my own, with no help from anyone else.

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1 point each. No partial credit.

1.   How long does it take to read a disk with 500 cylinders, each containing 6 tracks (there
     are 6 heads for the disk)? First, all of cylinder 0 is to be read, then all of cylinder 1, until all
     the cylinders have been read. Each track should be read starting at sector 0. The rotation
     time is 15 msec, and 1 track can be read during that rotation. A seek takes 10 msec
     between adjacent cylinders, and 25 msec in the worst case. Switching between tracks of a
     cylinder can be done instantaneously. Assume the heads are positioned at cylinder 0,
     sector 0 at the start of this process.

2.   How long does it take to read a disk with 500 cylinders, each containing 6 tracks (there
     are 6 heads for the disk)? First, all of surface 0 should be read from track 0 to track 499,
     then all of surface 1, from track 0 to track 499, then read all of surfaces 2 through 5, in the
     same way. Each track should be read starting at sector 0. The rotation time is 15 msec,
     and 1 track can be read during that rotation. A seek takes 10 msec between adjacent
     cylinders, and 25 msec in the worst case. Assume the heads are in the worst possible
     position at the start of this process.

For questions 3-6, Hamming Codeword means  the Hamming Codeword for single-bit error
correction with even parity in the check bits. 

3.   Calculate the Hamming Codeword for the following data word:

     11001100110

4.   Calculate the Hamming Codeword for the following data word:

     10001101000

5.   Determine if the following Hamming Codeword is correct. If it is correct, indicate what
     the original data word was. If it is incorrect, then correct it, and indicate what the
     corrected data word is.

     0110110111001016.   Referring to the timing diagram of Fig. 3-34 of the text, suppose that you slowed the
     clock down to a period of 400 nsec instead of 250 nsec as shown and the timing
     constraints changed to the following. How much time would the memory have to get the
                                                                  
     data onto the bus after MREQ was asserted, in the worst case?
                                
                                
     Symbol     Min       Max     Unit
     TAD                 130      nsec
     TML        75                nsec
     TM                   95	  nsec
     TRL		  95 	  nsec
     TDS	60		  nsec                                
     TMH		  95	  nsec                                
     TRH		  95	  nsec                                
     TDH	 0		  nsec                                

7.   Draw a circuit using as many AND, OR and NOT gates as necessary to implement the
     following:
                                    
     (not A)BC + A(not B)C + B(not C)

8.   Implement the above problem using a single MSI multiplexer chip.

9.   Draw a circuit using as many AND, OR and NOT gates as necessary to implement the
     following:
                            
     A(not B)C + AB(not C) + (not A)BC + A(not B)C

10.  Find an equivalent expression for the above and implement it using AT MOST THREE of
     the SSI chips on page 89 of the text. Show all connections.