Exam Time: Dec 9, 6:25 - 9:05
- Chapter 3
- Motorola Chips
- Differences and similarities between Motorola and Intel
- IBM PC Bus
- Bus Controller
- DMA Controller
- Interrupt Controller
- I/O Chips
- PIO Chips
- Address Decoding
- Full decoding
- Partial Decoding
- Chapter 4
- Microarchitecture
- Data Path
- Registers
- Latches
- ALU
- Shifter
- MAR
- MBR
- Control Signals
- Microinstructions
- AMUX
- COND
- ALU
- SH
- MBR
- MAR
- RD
- WR
- ENC
- C
- B
- A
- ADDR
- How do these affect the data path
- Microinstruction Timing
- 4 subcycles
- load MIR
- gate A and B latches
- ALU, SH, MAR
- store C and MBR
- Microinstruction Sequencing
- Conditional Jumps
- Unconditional Jumps
- Macroarchitecture
- Stacks use for variables, procedures, arguments, and locals
- Macroinstruction Set (don't memorize the binary)
- Translate macro to micro
- Translate micro to macro
- Microporgram
- Micro Assembly Language
- Translate Micro to Binary
- Translate Binary to Micro
- Example Microprogram
- Translate microinstruction groups to macroinstruction
- Design of Microprogramming Level
- Horizontal vs Vertical
- Nanoprogramming
- Improving Performance
- Pipelining - problems and solutions with pipelining
- Cache Memory
- Associative
- Direct-mapped
- Set Associative
- Examples of Microprogramming Level
- 8088
- pipelined - four units
- 8 or 16 bit operations
- 2 parts of data path
- 4 byte queue
- vertical
- 68000
- 16 or 32 bit operations
- 3 parts of data path
- pipelined - 3 units
- nanostore
- all microinstructions have a jump to next instruction
- Chapter 6, Operating System Level
- Virtual Memory
- Paging
- virtual address space
- physical address space
- page frame
- page table
- transparent to user
- page fault
- Page Replacement Policy
- Segmentation
- variable size
- user must manage segments
- Chapter 8, RISC
- Why RISC?
- Design Principles
- Analyze application
- Design data path for application
- Design instructions for data path
- Add new instructions only if machine is not slowed
- sacrifice everything to reduce data path cycle time
- One Instruction per Data Cycle
- LOAD/STORE architecture
- Pipelining
- No microcode
- Fixed-Format Instructions
- Reduced Instruction Set
- Put Complexity in Compiler
- Multiple Register Sets
- Register Allocation
- CISC vs RISC
- Which is better for high-level language programs
- How much gain is RISC, how much is large register file
- How good are RISC machines overall
- Which compilers are easier to write