Exam Time: Dec 8, 6:25 - 9:05

• Chapter 4
  • Microarchitecture
    • Data Path
      • Registers
      • Latches
      • ALU
      • Shifter
      • MAR
      • MBR
      • Control Signals
    • Microinstruction layout (Figure 4-9)
      • AMUX
      • COND
      • ALU
      • SH
      • MBR
      • MAR
      • RD
      • WR
      • ENC
      • C
      • B
      • A
      • ADDR
      • How do these affect the data path
    • Microinstruction Timing
      • 4 subcycles
        • load MIR
        • gate A and B latches
        • ALU, SH, MAR
        • store C and MBR
    • Microinstruction Sequencing
      • Conditional Jumps
      • Unconditional Jumps
      • Mmux logic
  • Macroarchitecture
    • Stack
      • Global variables
      • Procedure parameters
      • Local variables
      • Call and Return instructions
    • Macroinstruction Set (don't memorize the binary)
      • Translate macro to micro
      • Translate micro to macro
      • Be able to write a simple program in it
      • How can new instructions be added
  • Microprogram
    • Micro Assembly Language (Figure 4-15)
      • Translate Micro to Binary
      • Translate Binary to Micro
    • Example Microprogram (Figure 4-16)
      • Translate microinstruction group to macroinstruction
      • Translate macroinstruction to microinstruction group
  • Design of Microprogramming Level
    • Horizontal vs Vertical
      • Mic-2 opcodes (Figure 4-17)
      • Note the changes in the microarchitecture (Figure 4-18)
      • Understand the control signals (Figure 4-19)
    • Nanoprogramming, calculate savings
    • Improving Performance
      • Multiway jumping
      • Pipelining - problems and solutions with pipelining
        • Jump prediction
        • Out of order execution
      • Cache Memory
        • Associative
        • Direct-mapped
        • Set Associative
  • Examples of Microprogramming Level
    • 8088
      • pipelined - four units
      • 8 or 16 bit operations
      • 2 parts in the data path
      • 4 byte queue
      • vertical
    • 68000
      • 16 or 32 bit operations
      • 3 parts in the data path
      • pipelined - 3 units
      • nanostore
      • all microinstructions have a jump to next instruction
• Chapter 6, Operating System Level
  • Virtual Memory
    • Paging
      • virtual address space
      • physical address space
      • page frame
      • page table
      • transparent to user
      • page fault
      • calculate physical address from logical address
    • Page Replacement Policy
      • LRU
      • FIFO
    • Segmentation
      • variable size
      • user must manage segments
• Chapter 8, RISC
  • Why RISC?
  • Design Principles
    • Analyze application
    • Design data path for application
    • Design instructions for data path
    • Add new instructions only if machine is not slowed
    • sacrifice everything to reduce data path cycle time
    • One Instruction per Data Cycle
    • LOAD/STORE architecture
    • Pipelining
    • No microcode
    • Fixed-Format Instructions
    • Reduced Instruction Set
    • Put Complexity in Compiler
    • Multiple Register Sets
    • Register Allocation
  • CISC vs RISC
    • Which is better for high-level language programs
    • How much gain is RISC, how much is large register file
    • How good are RISC machines overall
    • Which compilers are easier to write