CDA4101, Computer Organization, Fall 1997 Syllabus

Instructor: Tim Downey
Office: BA 254B	Phone: 348-3329 (FIU-D-DAY)
Office Hours: Monday, Wednesday 3:45 - 4:45, 8:00 - 8:30	Tuesday, Thursday 1:25 - 1:55
E-mail downeyt@fiu.edu	Web http://www.cs.fiu.edu/~downeyt

Text:

Structed Computer Organization, Third Edition, Andrew S. Tannebaum, Prentice Hall, 1992.

Grading

Mid-term : 30%

Final : 30%

Homework : 40%

Exam Dates: Mid-term : Wednesday 10/8 Final : Monday 12/8, 1825 - 2105

Attendance

I recommend that you attend every class. Those who attend class have a better chance of passing the course.

Grading Policy

Each assignment is graded from 0 to 20 points Late Assignment Policy: You may hand in an assignment up to 24 hours late. You lose 2 points off the grade for every 12 hours. Programs are due at the START of class. After 24 hours, you may still hand in a program, but I will start the grading at 50%.

Working Together on Homework - NOT ALLOWED

There is a large difference between discussing general aspects of the course and discussing specific aspects of the homework. Do not discuss your solution of a problem with others. Assignments that are too similar will not be graded. A second occurrence will earn an F in the course.

Course Content

Multilevel Computers
The Conventional Machine Language Level
The Assembly Language/ Relocatable Level
- Relocatable Code
- Structure of an Assembler
- Structure of a Linking Loader
The Digital Logic
- Level Gates and Boolean Algebra
- Basic Digital Logic
- Circuits
- Memory
- Busses
The Microprogramming Level
- A Higher Level View of the Digital Logic Level
- An Example Macroarchitecture
- An Example Microarchitecture
- Vertical vs. Horizontal Microarchitectures
- Nano-programming
- Performance Optimazation
The Operating System Level
- Memory Management
- Cache Memory
- Real Memory Systems
- Virtual Memory Systems
- Paging
- Segmentation
- Virtual I/O Instructions
Advanced Computer Architectures
- Reduced Instruction Set Computers
  - Attributes of RISC Machines
  - The RISC Design Philosophy
  - Instruction Fetch/Decode/Execute
  - Pipelining
  - RISC vs. CISC
- Parallel and Dataflow Architectures
  - A Taxonomy
  - SIMD Computers
  - MIMD Computers
  - Dataflow Architectures