CDA4101, Fall 1998, Assignment 5

Due Monday 12/7 at the start of the exam

This homework is optional. You may use it to add to your homework average. If you do this assignment, then I will count all 5 homeworks when calculating your grade. If you don't do this assignment, then I will use only the first four when calculating your grade. If you do the assignment, then each homework will be 8% of your final grade instead of 10%.

1. (5 points) The microarchitecture from the book could be redesigned to allow a PLA to decode the instruction in the IR, instead of having the microprogram do it.
   1. How could the microarchitecture on page 176 be redesigned to allow this? In other words, where would the PLA go, and how would its output be enabled? Indicate how the timing of this would fit into the four subcycles.
   2. How would this affect the layout of the microinstruction on page 174? In other words, would any bits need to be added to allow the use of the PLA?
   3. How would this affect the microprogram? Indicate what types of instructions could be eliminated, and be sure to indicate how the microprogram accesses the output of the PLA.
2. (5 points) Suppose that JLESS and JGTR for signed numbers where added to the microarhitecture from the book. All other instructions would remain the same. For these two instructions only, the technique of section 4.5.3 will be implemented.
   1. How would the microarchitecture on page 176 be redesigned to add the C and V bits? Be specific about the hardware that would need to be added.
   2. How would the microarchitecture be redesigned to allow the ANDing of the low 4-bits of the address field with the 4 condition codes?
   3. How would this affect the layout of the microinstruction on page 174? In other words, would any bits need to be added to indicate when to allow the ANDing of the bits?
   4. How would this affect the microprogram? In other words, how would you implement these new instructions? You have to pick the addresses carefully. You may need to move some old instructions. Do not make the microprogram any bigger than it has to be.
3. (5 points) Suppose the pipelining technique for the microarchitecture of the book were implemented as described in the last part of section 4.5.4.
   1. Rewrite lines 30-34 on page 190 under this assumption.
   2. Rewrite lines 73 - 78 on page 191 under this assumption.
   3. Rewrite lines 5 - 10 on page 190 under this assumption.
4. (5 points) Consider the 24 bit address 089FE45h in hexadecimal notation.
   1. What would be the block number for this address in the associative cache on page 212?
   2. Suppose an eight-byte block were used. What would be the block number for this address in the associative cache on page 212?
   3. What would be the tag number and slot number for this address in the direct-mapped cache on page 213?
   4. Suppose an eight-byte block were used. What would be the tag number and slot number for this address in the direct-mapped cache on page 213?