Assignment 2

Due  5/24 at the start of class

1. (4 points) On many CPUs there are 4 condition codes: N, Z, O, C to test if the result of the ALU operation was zero, negative, wrong as a signed number, wrong as an unsigned number, respectively. An 8-bit ALU is constructed from 8 1-bit ALUs in Fig. 3-20. How would each of these condition codes be wired to such an ALU? Draw the circuits for each. (The O bit is set when the carry in to the highest ALU is different from the carry out of the highest ALU).
   
2. (3 points) The shifter on page 136 only has two functions: shift right and shift left. Modify it so that it can do four functions: arithmetic shift right, logical shift right, shift left, don't shift. The shifting done in the book is logical shifting: a 0 is placed into the S0 or S7 bit, depending on which way the shift goes. An arithmetic shift left is the same as a logical shift left, a 0 is placed into bit S7. An arithmetic shift right places D0 into both S0 and S1: it is duplicating the sign bit. A don't shift operation would send each data bit to the corresponding output: D0 to S0, D1 to S1, etc.
   
3. (3 points) An SR latch can also be built from two NAND gates, instead of two NOR gates. No other gates are needed.
   1. Draw such a circuit.
   2. Categorize as queiescent, unstable, set, or reset the following values for S and R
      1. S = 0 R = 0
      2. S = 1 R = 1
      3. S = 0 R = 1
      4. S = 1 R = 0
         
4. (3 points) The 4 X 3 memory of Figure 3-29 uses 22 AND gates and three OR gates. It also has 11 input, output, and control lines. Suppose the circuit were expanded to 512 X 32.
   1. How many AND gates would be needed?
   2. How many OR gates would be needed?
   3. How many pins would be coming into and out of the chip?
      
5. (2 points) Sometimes it is useful for an 8-bit ALU such as Fig. 3-20 to generate the constant -1 as output. Give two different ways this can be sone. For each way, specify the values of the six control signals.
   
6. (2 points) In round robin bus arbitration, each device gets the bus in turn: device 1, device 2, device 3, device 1, device 2, device 3, etc. If a particular device has not made a request, then the arbiter will grant the bus to the next device. How could such an arbitration scheme be implemented? Do not draw a circuit, just discuss how it could be done.
   
7. (1 point) The circuit of Fig. 3-26 is a flip-flop that is triggered on the rising edge of the clock. Modify this circuit to produce a flip-flop that is triggered on the falling edge of the clock.
   
8. (1 point) Referring to the timing diagram of Fig, 3-37, suppose that you slowed the clock down to 25 MHz instead of 40 MHz as shown but the timing constraints remained unchanged. How much time would the memory have to get the data onto the bus during T3 after NOT MREQ was asserted, in the worst case?
   
9. (1 point) Why is it IMPOSSIBLE for the Pentium II to work on a 32-bit PCI bus without losing any functionality? Be specific. (Think about the address lines on the Pentium II).