Summer A 2000, Computer Org, Assignment 4
Due Tuesday, June 20 at the start of class
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(4 points) In the example of address decoding in section 3.7.2, draw the
circuit for full address decoding if the PIO uses 4 bytes starting at 20K,
the EPROM is 8K and starts at address 48K, the Ram is 4K and starts at address
8K.
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(3 points) The instruction ISHR (arithmetic shift right) exists in JVM but
not in IJVM. It uses the top two values on the stack, replacing the top with
a single value, the result. The second from top word of the stack is the
operand to be shifted. Its content is shifted right by a value between 0
and 31 inclusive, depending on the value in the 5 least significant bits
of the top word on the stack (the other 27 bits of the top word are ignored).
The sign bit is replicated to the right for as many bits as the shift count.
Extend the microcode to include this instruction as part of IJVM. (Hint:
You will need to generate the number 31)
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(1 point) The IJVM INVOKEVIRTUAL instruction needs to know how many local
variables the method has. Why?
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(3 points) Draw a finite state machine for branch prediction that uses three
bits. It should only change predictions after three consecutive mispredictions.
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(3 points) Mic-3. Figure 4-33 on page 258 shows how the SWAP instruction
from Mic-2 would be sequenced in Mic-3. Create a similar table for ILOAD.
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(3 points) In Fig. 4-43, suppose that I6 was R5 = R0 - R2. Indicate which
instructions could be issued and which could be retired in each cycle from
cycle 6 forward. There will be fewer cycles to complete all the instructions.
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(3 points) Consider the direct-mapped cache on page 267.
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What would be the tag and line for the hex address 7900EF3Dh?
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If the number of bytes in a word were doubled to 8 and there were the same
number of lines in the cache, what would be the tag and line for the
direct-mapped cache?