Assignment 2

Due 5/19 at the start of class

1. The shifter on page 96 only has two functions: shift right and shift left. Modify it so that it can do four functions: arithmetic shift right, logical shift right, shift left, don't shift. The shifting done in the book is logical shifting: a 0 is placed into the S0 or S7 bit, depending on which way the shift goes. An arithmetic shift left is the same as a logical shift left, a 0 is placed into bit S7. An arithmetic shift right places D0 into both S0 and S1: it is duplicating the sign bit.
   
2. Whatever is done in software can be done in hardware. On the PC, subtraction is done in software, but the designers of the 8088 could have included a subtraction unit in the CPU. It is very similar to the adder. One difference is that the Carry lines are called the Borrow lines. There are other differences, too.
   1. Draw the circuit for a half-subtractor.
   2. Draw the circuit for a full-subtractor.
      
3. The ALU on page 99 has four functions: A ADD B, A AND B, A OR B, NOT B. Redraw it so that it has all of the old functions, plus A SUB B, A (just move A through the circuit), A COMPARE B (test if A and B are equal), A ADD 1. If you didn't do number 2, then just indicate an empty box for the subtraction circuit, and indicate how it is selected, and what lines go into it. If you did number 2, then you might see a way to simplify the ALU without including a complete, separate circuit for subtraction (or maybe not). You might need a large piece of paper for this one.
   
4. An SR latch can also be built from two NAND gates, instead of two NOR gates.
   1. Draw such a circuit.
   2. What are the normal states for S and R when the circuit is quiescent (not changing)?
   3. What are the states for S and R that should be avoided, because they make the output of the circuit random?
      
5. The 4 X 3 memory of Figure 3-28 uses 22 AND gates and three OR gates. It also has 11 lines into it. Suppose the circuit were expanded to 256 X 8.
   1. How many AND gates would be needed?
   2. How many OR gates would be needed?
   3. How many lines would be needed?
      
6. A computer with a 32-bit wide data bus uses 1M X 4 dynamic RAM chips. What is the smallest memory (in bytes) that this computer can have?
   
7. Referring to the timing diagram of Figure 3-34, suppose that you slowed the clock down to a period of 400 nsec instead of 250 nsec as shown but the timing constraints remained unchanged. How much time would memory have to get the data onto the bus after NOT MREQ was asserted, in the worst case?
   
8. Most 32-bit buses permit 16-bit reads and writes. Is there any ambiguity about where to place the 16 bits of data onto the 32-bit bus? Discuss.