Summer 1999 CDA4101 Daily Coverage

I have a good intention of keeping this page updated.

5/3

Syllabus, computer levels, virtual machine, generations, RISC vs CISC, pipelining, super-scalar

5/4

Transistors, NOT, NAND, NOR, AND, OR, XOR, Boolean algabra, majority function, boolean functions, circuit equivalence

5/5

Integrated circuits, gate delay, combinational circuits, multiplexer, decoder, comparator, MSI multiplexer, implementing 3-input and 4-input boolean functions on a MSI multiplexer, PLA, shifter, demultiplexer

5/6

Half-adder, full-adder, propogation delay (ripple carry adder/carry select adder), ALU, 8-bit ALU, propogation delay, clock, generating an asymmetric pulse from a symmetric pulse, S-R latch

5/10

Clocked SR-latch, clocked D-latch, flip-flops (edge and level triggered), pulse generator, D flip-flop, D latches and flip-flops, registers, memory organization, logic diagram of a 4x3 memory, tri-state devices

5/11

Memory chips, orgainizing 4-Mbit memory, RAS, CAS, address lines determine the number of addresses on a chip, SRAM, DRAM, FPM, EDO, SDRAM, ROM, PROM, EPROM, EEPROM, flash memory, 6 categories of pins on a CPU, types of computer buses

5/12

PC bus, PC/AT bus, Microchannel bus, ISA bus, EISA bus, Synchronous bus, Asynchronous bus, Bus arbitration, Centralized and decentralized arbitration, Single-level daisy chaining

5/13

Multi-level daisy chaining with arbiter, Decentralized daisy chaining, Round Robin, Priority levels, Bus operations, Block transfers, Read-modify-write cycle, Interrupts, Pentium II characteristics, Pentium II pinout

5/17

Pipelining on the Pentium II, 6 phases of the pipeline, UltraSPARC II characteristics, SBus, UPA, UDB II, picoJava II charactersistics

5/18

PCI Bus characterstics, architecture of the Pentium II and how the PCI bus fits, PCI Bus Arbitration, PCI Bus Signals (AD, C/BE, FRAME, IRDY, DEVSEL, TRDY), PCI Bus Transactions (read and write), Universal Serial Bus characteristics, frame types, packet types

5/19

PIO chip, Address Decoding, The Data Path we will consider, discussion of next homework assignment

5/20

The Data Path again, ALU functions, Data Path Timing, Memory Operation, Microinstructions, Conditional Branches

5/24

Review

5/25

Midterm

5/26

Conditional branches (JAMN and JAMZ), Complete block diagram for Mic-1, MPC, MIR, Timing of the instruction cycle

5/27

Stack machine, arithmetic on a stack machine, IJVM memory model, IJVM instruction set, Compiling to IJVM

6/2

Notation for a microinstruction, Implementation of IJVM using Mic-1

6/3

Continuation of the implementation, The stack when calling a method, The stack when returning from a method

6/4

Speed versus cost, reducing the execution path length, merging the interpreter loop, 3-bus architecture, IFU

6/7

IFU continued, MBR1, MBR2, IMAR, Mic-2 data path, Mic-2 microprogram, Adding the A, B, and C latches, pipelining using Mic-3, RAW, WAR

6/8

Mic-4, Cache Memory

6/9

Write through, Write back (deferred), Write allocate, Dynamic and static branch prediction

6/10

FSM for 2-bit branch prediction, RAW, WAR, False dependencies, Register renaming, Out-of-Order Execution, Speculative Execution, basic blocks, hoisting, poison bit

6/14

Pentium II microarchitecture, Sparc microarchitecture, picoJava microarchitecture, instruction folding, comparison of the three architectures, Chapter 5: Memory models, registers, Pentium II ISA level, SPARC ISA level, Java ISA level

6/15

Input/Output, programmed I/O, busy waiting, DMA, IA-64 model, Explicitly Parallel instructions, predication, speculative loads

6/16

Review

6/17

Final

1. What is your name?
2. What is your favorite color?
3. ...