Spring 1999, Computer Org, Assignment 4

Due Wednesday 4/7 at the start of class

1. (4 points) In figure 3-56 on page 195, what would be the full address decoding for the following schemes?
   1. Assume that the EPROM starts at address 56K, the RAM starts at address 16K, and the PIO is the last 4 bytes before 32K.
   2. Assume that the EPROM is 4K in size and starts at address 24K, the RAM is 8K and starts at address 48K, and the PIO is 4 bytes starting at 4K
2. (4 points) In the microprogram on page 234,
   1. What would be the hex machine code for the iand3 instruction? Assume the next address in binary is 100010001.
   2. What would be the MAL code for the hex machine code of
      0003604A4
3. (5 points) Translate the following high level language code into IJVM. Assume that count and answer are integers and that calculate is a function of two integer arguments returning an integer. Assume that the return value from the function will be on top of the stack upon return from the function. Push a value of 0 on the stack for OBJREF before pushing the parameters on the stack for the call to calculate.

   total = 0;
   for (count = 0; count < 10; count++) {
   	answer = calculate( count, 10);
   	if (answer > 0) {
   		total += answer;
   	}
   }
   
   

4. Suppose that a C and a V bit were added to the hardware, in addition to the N and Z bits. The C bit means that the answer didn't fit in 32 bits, the C bit is the 33 bit when the numbers are viewed as unsigned. The V bit means that the sign of the answer is incorrect when the numbers are viewed as signed numbers.
   1. (2 points) How would the C and V bits be implemented in hardware, if the ALU is made of 32 1-bit ALUs? Draw a circuit diagram for each. You may use boxes for the 1-bit ALUs, but you must label all lines that you use. The V bit will be set when the carry out of the highest bit is different form the carry out of the second highset bit.
   2. (1 point) Sometimes it is preferable to leave the condition codes N, Z, C, and V unchanged by the ALU. How would the architecture have to be changed in order to prevent some instructions from changing the condition codes?
   3. (4 points) Assume that your designs from parts a and b have been implemented. Now it is possible to have MAL branch instructions that only test the condition codes, they will not set them. There would be four of these branch instructions.
      if (N) goto dest
      if (Z) goto dest
      if (V) goto dest
      if (C) goto dest
      Where dest can be any label in the microprogram (T, F, or any other label). Each could also have an optional else, that could also jump to any label in the microprogram.
      You may also assume that there are versions of all MAL instructions that do not change the condition codes (like TOS = MDR, NC or SP = SP + 1, NC where NC means No Change to the condition codes).
      What would be the MAL statements to implement each of the following new IJVM instructions?
      1. IF_ICMPGT offset: pop two words off the stack, jump if the top number on the stack is greater than the second number on the stack. Do not leave any temporary values on the stack when the instruction is done. Compare the numbers as signed 2's-complement numbers. You must test the Z, V, and N bits. Do a subtraction and test the result.
      2. IF_ICMPLTU offset: pop two words off the stack, jump if the top number on the stack is less than the second number on the stack. Do not leave any temporary values on the stack when the instruction is done. Compare the numbers as unsigned numbers. You must test the C and Z bits. Do a subtraction and test the result.