Spring 1999, Computer Org, Assignment 5
Answers
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No circuits on test
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No circuits on test
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(4 points) Mic-2
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Explain in detail why INVOKEVIRTUAL is only 11 instructions
in Mic-2, but 22 instructions in Mic-1. Indicate why some instructions could
be combined, and why some instructions could be eliminated altogether.
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invokevirtual1,7,10,13,21 are eliminated because IFU does all fetching
and PC incrementing
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invokevirtual2-4 combined into 1 instruction: MAR = CPP + MBRU2 due to IFU
and additional bus
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invokevirtual5 becomes OPC = PC because IFU increments PC
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invokevirtual6 becomes PC = MDR becuase IFU does all fetching
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invokevirtual8,9,11 combined into TOS = SP - MBRU2 due to IFU and additional
bus
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invokevirtual12 beomes TOS = MAR = H = TOS + 1 because H is needed as temp
reg
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invokevirtual14,15,16 combined into MDR = SP + MBRU2 + 1 due to IFU and
additional bus
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invokevirtual17-20 remain unchanged, but have different labels
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invokevirtual22 becomes LV = TOS; goto (MBR1) due to merging the interpreter
loop and the IFU.
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Do the same analysis for ILOAD.
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iload1,2 combined into MAR = MBRU1 + LV; rd due to IFU and additional bus
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iload3 unchanged but with new label
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iload4 is not needed dut to IFU doing all fetching and incrementing PC. wr
is moved to next instruction
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iload5 besomes TOS = MDR; wr; goto (MBR1) due to merging the interpreter
loop and the IFU and moving wr from previous instruction to this instruction.
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(2 poionts) Whenever the ALU does subtraction for unsigned
numbers, it inverts the normal carry out bit to set the carry flag. How would
this be implemeted in hardware?
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AND the ENB, ENA, INVA, and INC input lines of the ALU. XOR the result with
the carry out of the high bit. This will toggle the carry out whenever B-A
is performed.
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(2 points) It is not reliable to use the N bit to determine
the relative order of two unsigned numbers. Give me an example of subtracting
unsigned numbers as follows:
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Perform A - B where the result is negative and A < B.
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perform C - B where the result is positive and C < B. B should be the
same number as in the first subtraction.
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(4 points) Mic-3. Figure 4-33 on page 258 shows how the SWAP instruction
from Mic-2 would be sequenced in Mic-3.
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Create a similar table for ILOAD.
iload1 |
iload2 |
iload3 |
A=LV; B=MBRU1 |
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C = A + B |
B = SP |
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MAR = C; rd |
C = B + 1 |
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MDR = mem |
MAR = SP = C |
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B = MDR |
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C = B |
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TOS = C; wr |
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Create a similar table for IRETURN
ireturn1 |
ireturn3 |
ireturn4 |
ireturn5 |
ireturn6 |
ireturn7 |
ireturn8 |
B = LV |
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C = B |
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MAR=SP=C;rd |
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MDR = mem |
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B = MDR |
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C = B |
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LV=MAR=C;rd |
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MDR = mem |
B=LV |
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C=B+1 |
B=MDR |
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MAR=C |
C=B |
B=SP |
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PC=C;rd |
C=B |
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MDR=mem |
MAR=C |
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B=MDR |
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C=B |
B=TOS |
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LV=C |
C=B |
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MDR=C;wr |
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goto(MBR1) |
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(2 points) Consider the direct-mapped cache on page 267.
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What would be the tag and line for the hex address
087F473ADh?
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87F473AD
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1000 0111 1111 0100 0111 0011 1010 1101
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10000111111101000111001110101101
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1000011111110100 01110011101 011 01
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Tag: 1000011111110100
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Line: 01110011101
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Word: 011
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Byte: 01
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If this were a full associative cache, then what would
be the tag and the line for the same address?
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87F473AD
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1000 0111 1111 0100 0111 0011 1010 1101
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10000111111101000111001110101101
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100001111111010001110011101 011 01
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Tag: 100001111111010001110011101
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Word: 011
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Byte: 01