Computer Organization, Homework 3

Due Wednesday, 11/25

1. How long does a 2GHzMic-1 take to execute the following Java instruction?

   i = j - k
   

2. Write the code for IINC_W. It behaves like IINC, but the offset to the local variable and the constant are both 16 bits.
3. Write the code fo IDIV2. It divides the top operand on the stack by 2 and overwrites the top of the stack with the result.
4. Implement IST_ARRAY in Mic-1. It is just like ISTORE except that it has an extra byte that is the number words on the stack to store into consecutive local variables.

   IST_ARRAY varnum byte

   The instruction will store byte number of words from the stack into consecutive local variables, starting with local variable varnum.

   Use symbolic names in conditional branch statements, but supply a table that gives hex addresses for each of these labels. Be sure all the labels have consistent addresses.

5. There are three improvements from MIC-1 to MIC-2:
   1. 3 bus architecture,
   2. instruction fetch unit handles the PC and can access 16-bit operands,
   3. merging the interpreter loop.

   INVOKEVIRTUAL in MIC-1 has 22 lines of code, it has 11 lines of code in MIC-2. There are three types of changes:

   1. sequences of instructions are grouped into one instruction,
   2. some instructions are removed,
   3. some instructions are modified.

   For the MIC-1 INVOKEVIRTUAL command,

   1. indicate which instructions are unchanged, removed, grouped, or modified.
   2. indicate which of the three improvements allowed the alteration. There could be more than one per line.
   3. If they are grouped, modified or unchanged, indicate the corresponding instruction from Mic-2.

   If there is a choice between marking a statement as being grouped with others or being removed, choose grouped.

   Correction: line 5 in Mic-2 should be the same as line 12 in Mic-1. H does not needed to be updated in line 5 of Mic-2.

6. Create a table similar to the one in Figure 4-44 for the instructions below.
   R3 = R0 / R2
R3 = R3 * R2
R2 = R0 + R1
R0 = R2 / R5
R6 = R3 - R6
R3 = R8 + R0
   You do not need to indicate the scoreboard for the registers being read and written. Use out-of-order issue and out-of-order retire, with register renaming. Assume that the secret registers are S0 through S8.
   1. Add a column that indicates the type of dependency, if there is one. If there is more than one, list them all.
      • No Dependency
      • RAW
      • WAR
      • WAW
   2. Add a column for renamed registers. List how a register was renamed, like S3 = R3.
7. Consider the direct-mapped cache in Figure 4-38 for the address 0xFEB43265.
   1. What would be the tag and line for this address ? Leave your answers in hex. Show your work.
   2. Suppose the number of bytes in a word were doubled to 8, that there were twice as many lines in the cache, and that there were 16 words in a line. What would be the tag and line for this address? Leave your answers in hex. Show your work.

Quiz

The quiz for this homework will be on Monday, November 30.